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? semiconductor components industries, llc, 2015 august, 2015 ? rev. p4 1 publication order number: ncp6868/d ncp6868 product preview 2.5 a boost regulator with bypass function the ncp6868 is a synchronous boost converter. it is designed primarily to boost new generation low-voltage li-ion batteries (silicon anode-like) embedded into cell and smart phones. the objective is to guarantee a minimum output voltage even in the case for which the battery voltage is below the minimum voltage required by the system. the device features a bypass mode coupled with a boost mode. it is capable to drive a continuous load up to 2.5 a and it operates at a switching frequency of 2.5 mhz. an i 2 c serial control can also be enabled for configuring the output voltage and peak current limit. the ncp6868 is available in a space saving, low profile 1.8 1.8 mm csp-16 package. features ? 2.35 v to 5.5 v input voltage ? fixed or programmable v out : from 2.85 v up to 5.3 v ? bypass operation when v in is above or close to v out ? few external components & 0.47 h inductor ? high efficiency up to 98% ? output current up to 2.5 a continuous (v in = 2.6 v, v out = 3.5 v) and up to 4 a peak current ? inductor peak current up to 9.0 a ? forced bypass option through bp pin ? low quiescent current: 50 a ? voltage control pin (vsel) to precisely adjust v out ? i 2 c serial control as a software-mode option to program output voltage and peak current limit ? soft-start function (ss) to limit inrush current ? current limitation to protect against short circuit ? thermal limit protection ? small 1.8 1.8 mm / 0.4 mm pitch csp package ? these devices are pb?free and are rohs compliant typical applications ? boost converters for new generation low-voltage li-ion batteries ? usb otg (on-the-go) ? 3g/4g ? lte rf pa ? cell phones, smart phones, phablets, tablets & webtablets this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. 6868x = specific device code x = p: ncp6868p b: ncp6868v315 c: ncp6868v330 e: ncp6868e315 a = assembly location l = wafer lot yy = year ww = work week = pb-free package marking diagram 6868x alyyww see detailed ordering and shipping information on page 27 o f this data sheet. ordering information wlcsp16 case 567ju www.onsemi.com
ncp6868 www.onsemi.com 2 typical application figure 1. application block diagram figure 2. pin out (top view) 1.80 mm 1.80 mm a1 en a2 pg a3 pvin a4 pvin d1 agnd d2 pgnd d3 pgnd d4 pgnd b1 vsel b2 nc/scl b3 vout b4 vout c1 bp c2 nc/sda c3 sw c4 sw pin out
ncp6868 www.onsemi.com 3 table 1. pin function description pin name type description a1 en input enable control. active high will enable the part. there is an internal pull down resistor on this pin. a2 pg input/output interrupt output pin active low (open drain); pg is pulled low if a pg event is detected that is output out of regulation, over-voltage, overload, uvlo or twrn protection is activated. pg is pulled-up high when en is low. a3?a4 p vin power input dcdc input power connected to a li-ion battery. this pin must be decoupled to ground by a 10 f and 1 f ceramic capacitors. these capacitors should be placed as close as possible to this pin. b1 vsel input output voltage select. this pin can be used to select the voltage when the device operates in boost mode. vsel = low, low voltage target selected; vsel = high, high voltage target selected. there is an internal pull-down resistor on this pin. b2 mode/scl input mode: b2 pin is configured as a mode pin when the i 2 c interface is disabled and the device output voltage is fixed. when mode = low the device is operating in auto mode. this pin must be set low during device start-up. when mode = high the device is operating in forced ccm mode. scl: i 2 c interface clock line when the i 2 c interface is enabled. there is an internal pull down resistor on this pin . c2 nc/sda ground or input/output nc: for device without i 2 c interface activated, connect this pin to agnd. sda: bidirectional data line of the i 2 c bus. d1 agnd ground analog ground. analog and digital circuit blocks? ground. this pin must be connected to the system ground. b3?b4 v out power output output voltage. connect output capacitors as close as possible to the device. c1 bp input bypass pin. active low. this pin is used to force the device into the bypass mode. in forced bypass mode, both bypass p-mosfet and p-channel mosfet (see figure 1) are turned on and n-channel mosfet (see figure 1) is turned off. there is an internal pull-up resistor on this pin. c3?c4 sw power dc-dc switch power pin. this pin connects the power transistors to one end of the inductor. typical application (2.5 mhz) uses a 0.470 h inductor; refer to application section for more information. d2?d4 pgnd ground power ground. this pin is the power ground and carries the high switching current. high quality ground must be provided to prevent noise spikes. to avoid high-density current flow in a limited pcb track, a local ground plane that connects all pgnd pins together is recommended. analog and power grounds should only be connected together in one location through a printed trace. table 2. modes of operation en bp device state 0 x all bias circuits are off and the device is in shutdown mode. during shutdown, current flow is prevented from p vin to v out and from sw to v out . 1 0 the device is active and forced in bypass mode. a short circuit protection is embedded in order to prevent the output voltage going to low. 1 1 the device will switch between boost mode and bypass mode automatically.
ncp6868 www.onsemi.com 4 table 3. maximum ratings rating symbol value unit analog and power pins: p vin , sw v a ?0.3 to +6.0 v v out pin v out ?0.3 to +6.0 v digital pins: en, vsel, bp , mode/scl, sda, pg: input voltage input current v dg i dg ?0.3 to v a + 0.3 6.0 10 v ma operating ambient temperature range t a ?40 to +85 c operating junction temperature range (note 1) t j ?40 to +125 c storage temperature range t stg ?65 to + 150 c maximum junction temperature t jmax ?40 to +150 c thermal resistance junction-to-ambient (note 2) r ja 78 c/w esd, electrostatic discharge protection, human body model (note 3) charged device model hbm cdm 2 1 kv latch up current: (note 4) digital pins all other pins i lu 10 100 ma moisture sensitivity (note 5) msl level 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the thermal shutdown set to 150 c (typical) avoids potential irreversible damage on the device due to power dissipation. 2. the junction-to-ambient and junction-to-board thermal resistances are a function of printed circuit board (pcb) layout and ap plication. these data are measured using 4-layer pcbs (2s2p). for a given ambient temperature t a it has to be pay attention to not exceed the max junction temperature t jmax . 3. this device series contains esd protection and passes the following ratings: human body model (hbm) 2.0 kv per jedec standard: jesd22?a114. machine model (mm) 150 v per jedec standard: jesd22?a115. 4. latch up current per jedec standard: jesd78 class ii. 5. moisture sensitivity level (msl): 1 per ipc/jedec standard: j?std?020a. table 4. recommended operating conditions symbol parameter conditions min typ max unit p vin power supply (note 6) 2.35 ? 5.5 v v out v out range 2.85 ? 5.3 v v out fixed output voltage for standard versions other output voltages in the range 3 v to 5.3 v are available by request. ncp6868v315 vsel low ? 3.15 ? v vsel high ? 3.35 ? v ncp6868v330 vsel low ? 3.30 ? v vsel high ? 3.50 ? v ncp6868e315 vsel low ? 3.15 ? v vsel high ? 3.60 ? v ncp6868p vsel low ? p* ? v vsel high ? p* ? v i out continuous output current for v out 3.5 v and p vin 2.5 v 0 ? 2.5 a i loadstartmax maximum load current during start-up 500 ma l inductor for dcdc converter (note 7) ? 0.47 ? h c o output capacitor for dcdc converter (note 7) 15 20 56 f c in input capacitor for dcdc converter (note 7) 3.3 4.7 ? f functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. * p = programmable. 6. operation above 5.5 v input voltage for extended period may affect device reliability. 7. including de-ratings (refer to application information section of this document for further details)
ncp6868 www.onsemi.com 5 electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. p vin = 2.35 v to v out (unless otherwise noted). typical values are referenced to p vin = 3.0 v, t a = +25 c and default configuration (figure 1) (note 8) symbol parameter conditions min typ max unit supply current: pin p vin i qbp operating quiescent current, bypass mode (auto) v out = 3.5 v, p vin = 3.7 v ? 30 50 a i qboost operating quiescent current, boost mode v out = 3.5 v, p vin = 3.2 v ? 55 70 a i sd shutdown current en = low, p vin = 3.0 v ? 1 5 a i qbpforced forced bypass mode v out = 3.5 v, p vin = 3.5 v low iq ? 3 8 a v out = 3.5 v, p vin = 3.5 v ocp on ? 25 40 a dcdc converter p vin input voltage range 2.35 ? 5.5 v v out_acc output voltage accuracy referred to gnd, dc, v out ?p vin > 100 mv ?2 ? 4 % i outmax boost mode for v out 3.5 v and p vin 2.5 v ? ? 2.5 a p vinmin2.5a minimum p vin for 2.5 a load v out = 3.5 v, t j < 120 c ? 2.5 ? v v out = 3.15 v, t j < 120 c ? 2.35 ? v p vinmin2a minimum p vin for 2a load v out = 5.0 v, t j < 120 c ? 3.0 ? v v out = 4.5 v, t j < 120 c ? 2.8 ? v i lkout-in v out to p vin reverse leakage current v out = 5 v, en = low ? 0.2 1 a i lkout v out leakage current v out = 0 v, en = low, p vin = 4.2 v ? 0.1 1 a f sw switching frequency p vin = 3.0 v, v out = 3.35 v, i out =1a 2 2.5 3 mhz r onpmos p-channel mosfet on resistance (synchronous rectifier) from sw to v out , v out = 3.5 v, p vin = 3.5 v ? 30 60 m r onnmos n-channel mosfet on resistance (boost switch) from sw to pgnd, v out = 3.5 v, p vin = 3.5 v ? 25 50 m r onbp bypass p-mosfet on resistance from p vin to v out , v out = 3.5 v, p vin = 3.5 v ? 35 60 m load tr load transient response p vin = 3.0 v, v out = 3.5 v, i out = 500 to 1500 ma, t r =t f = 0.1 s ? 4 ? % i pklim boost peak current limit p vin = 2.6 v ? 5.0 9.0 a i ss_pklim boost peak current limit at soft-start p vin = 2.6 v ? 2.0 ? a iss pk soft-start input peak current limit ? 1600 ? ma ts s soft-start en high to regulation 50 load, c out =2x10 f ? 400 500 s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 8. guaranteed by characterization and design.
ncp6868 www.onsemi.com 6 electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. p vin = 2.35 v to v out (unless otherwise noted). typical values are referenced to p vin = 3.0 v, t a = +25 c and default configuration (figure 1) symbol parameter conditions min typ max unit control pins: en, bp , vsel v ih positive going input high voltage threshold 1.2 ? ? v v il negative going input low voltage threshold ? ? 0.4 v r pdown pull down internal resistor at control pins (en & vsel) ? 40 ? m r pup pull up internal resistor at /b/p pin ? 10 ? m i 2 c protocol v i 2 cint high level at scl/sda line 1.7 ? 5.0 v v i 2 cil scl, sda low input voltage scl, sda line (notes 9, 10) ? ? 0.5 v v i 2 cih scl, sda high input voltage scl, sda line (notes 9, 10) 0.8 x v i 2 cint ? ? v v i 2 col sda low output voltage sda pull up current = 3 ma (note 10) ? ? 0.4 v f scl i 2 c clock frequency (note 10) ? ? 3.4 mhz power good pin: pg v olpg power good pin low voltage level i pg = 5 ma ? ? 0.4 v ilk pg power good pin leakage current v pg = 5 v ? ? 1 a protections features v uvlo_fall under voltage lockout threshold p vin falling 2.25 2.30 2.35 v v uvlo_rise under voltage lockout threshold p vin rising 2.5 2.6 2.65 v v uvlohys under voltage lockout hysteresis ? 300 ? mv v ovp output over-voltage protection threshold ? 5.7 6.0 v v ovphys output over-voltage protection hysteresis (note 10) ? 250 ? mv t pgact pg pin activation temperature threshold (twarn) ? 120 ? c t pgrel pg pin release temperature threshold ? 100 ? c t sd thermal shut down protection ? 150 ? c t sdh thermal shut down hysteresis ? 20 ? c t rst fault restart timer ? 20 ? ms product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 9. devices that use non-standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the vdd voltage to which the pull-up resistors rp are connected. 10. guaranteed by characterization and design.
ncp6868 www.onsemi.com 7 typical operating characteristics (supply currents) v out = 3.5 v, l = 0.47 h, c out = 2 22 f, c in = 10 f, t a = 25 c (unless otherwise noted) figure 3. shutdown current vs input voltage figure 4. quiescent current in forced bypass mode (ocp off) vs input voltage figure 5. quiescent current in forced bypass mode (ocp on) vs input voltage figure 6. boost quiescent current vs input voltage figure 7. v out ripple vs output current figure 8. frequency vs i out for v out = 3.35 v 2.3 p vin (v) 3.1 0.0 i sd ( a) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 p vin (v) 0 1 2 3 4 5 6 7 8 9 10 2.3 p vin (v) 2.7 4.3 5.5 0 i qbpforced ( a) 5 10 15 20 30 25 2.3 p vin (v) 3.1 5.5 0 i qboost ( a) 10 20 30 40 90 50 2.7 4.7 60 500 i out (ma) 0.0 f sw (mhz) 0.5 1.0 1.5 2.0 2.5 1000 3.0 1500 2000 250 0 2.7 2.3 3.1 3.9 5.5 2.7 4.7 4.3 5.1 3.5 +85 c +25 c ?40 c i qbpforced ( a) 3.9 5.5 4.7 4.3 5.1 3.5 +85 c +25 c ?40 c 40 35 3.1 3.5 3.9 4.7 +85 c +25 c ?40 c 5.1 4.3 3.5 3.9 0 i out (ma) 500 0 ripple (mv) 10 100 +85 c +25 c ?40 c 1000 2500 1500 2000 vout = 3.15 v vout = 3.35 v vout = 3.5 v 5.1 70 80 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 3 2 1 3 2 1
ncp6868 www.onsemi.com 8 typical operating characteristics (efficiency) l = 0.47 h (tfm type), c out = 3 22 f, c in = 10 f, t a = 25 c (unless otherwise noted) figure 9. efficiency vs output current, p vin with v out = 3.15 v figure 10. efficiency vs output current, p vin with v out = 3.5 v 1 i out (ma) 100 70 efficiency (%) 75 80 85 90 95 10 1000 100 p vin = 3.1 v p vin = 3.0 v p vin = 2.6 v 1 i out (ma) 100 70 efficiency (%) 75 80 85 90 95 10 1000 100 p vin = 3.1 v p vin = 3.0 v p vin = 2.6 v 1 2 3 1 2 3 1 2 3 1 2 3 l = 0.47 h (spm type), c out = 3 22 f, c in = 10 f, t a = 25 c (unless otherwise noted) figure 11. efficiency vs output current, p vin with v out = 3.15 v figure 12. efficiency vs output current and temperature p vin = 3.0 v and v out = 3.15 v figure 13. efficiency vs output current, p vin with v out = 3.3 v figure 14. efficiency vs output current and temperature p vin = 3.0 v and v out = 3.3 v 1 i out (ma) 100 70 efficiency (%) 75 80 85 90 95 10 1000 100 p vin = 3.1 v p vin = 3.0 v p vin = 2.6 v 1 i out (ma) 100 70 efficiency (%) 75 80 85 90 95 10 1000 100 +85 c +25 c ?40 c 1 i out (ma) 100 70 efficiency (%) 75 80 85 90 95 10 1000 100 p vin = 3.1 v p vin = 3.0 v p vin = 2.6 v 1 i out (ma) 100 70 efficiency (%) 75 80 85 90 95 10 1000 100 +85 c +25 c ?40 c 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3
ncp6868 www.onsemi.com 9 typical operating characteristics (efficiency) l = 0.47 h (spm type), c out = 3 22 f, c in = 10 f, t a = 25 c (unless otherwise noted) figure 15. efficiency vs output current, p vin with v out = 3.35 v figure 16. efficiency vs output current and temperature p vin = 3.0 v and v out = 3.35 v figure 17. efficiency vs output current, p vin with v out = 3.5 v figure 18. efficiency vs output current and temperature p vin = 3.0 v and v out = 3.5 v 1 i out (ma) 100 70 efficiency (%) 75 80 85 90 95 10 1000 100 p vin = 3.1 v p vin = 3.0 v p vin = 2.7 v 1 i out (ma) 100 70 efficiency (%) 75 80 85 90 95 10 1000 100 +85 c +25 c ?40 c 1 i out (ma) 100 70 efficiency (%) 75 80 85 90 95 10 1000 100 p vin = 3.1 v p vin = 3.0 v p vin = 2.6 v 1 i out (ma) 100 70 efficiency (%) 75 80 85 90 95 10 1000 100 +85 c +25 c ?40 c figure 19. efficiency vs output current, p vin with v out = 3.6 v figure 20. efficiency vs output current and temperature p vin = 3.0 v and v out = 3.6 v 1 i out (ma) 100 70 efficiency (%) 75 80 85 90 95 10 1000 100 p vin = 3.1 v p vin = 3.0 v p vin = 2.6 v 1 i out (ma) 100 70 efficiency (%) 75 80 85 90 95 10 1000 100 +85 c +25 c ?40 c 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3
ncp6868 www.onsemi.com 10 typical operating characteristics (start up and shut down) l = 0.47 h (tfm type), c out = 3 22 f, c in = 10 f, t a = 25 c (unless otherwise noted) figure 21. power-up response, 50 load, v out = 3.3 v figure 22. power-down response, 50 load, v out = 3.3 v figure 23. power-up response, 50 load, v out = 3.5 v figure 24. power-down response, 50 load, v out = 3.5 v figure 25. power-up/down response in forced bypass mode, p vin = 3.0 v, 25 load figure 26. power-up/down response in forced bypass mode, p vin = 3.0 v, 50 load 100 s/div with 100 ns/pt 100 s/div with 100 ns/pt 2.0 ms/div with 10 ns/pt v en (2 v/div) v out (1 v/div) i in (500 ma/div) v en (2 v/div) v out (1 v/div) i in (500 ma/div) v en (2 v/div) v out (1 v/div) p vin (2 v/div) v en (2 v/div) v out (1 v/div) i in (500 ma/div) v en (2 v/div) v out (1 v/div) i in (500 ma/div) v en (2 v/div) v out (1 v/div) p vin (2 v/div) 100 s/div with 100 ns/pt 100 s/div with 100 ns/pt 2.0 ms/div with 10 ns/pt
ncp6868 www.onsemi.com 11 typical operating characteristics (dynamic transition) l = 0.47 h (tfm type), c out = 3 22 f, c in = 10 f, t a = 25 c (unless otherwise noted) figure 27. bypass entry/exit, slow p vin ramp 1 ms edge p vin = 3.2 v to 3.8 v, i out = 500 ma & v out = 3.5 v figure 28. vsel step p vin = 3 v, i out = 500 ma & v out = 3.5 v 3.7 v p vin (200 mv/div) offset: 3.5 v v out (200 mv/div) offset: 3.5 v 100 s/div with 100 ns/pt 100 s/div with 100 ns/pt v sel (2 v/div) v out (40 mv/div) offset: 3.3 v typical operating characteristics (load transient responses) l = 0.47 h (tfm type), c out = 3 22 f, c in = 10 f, t a = 25 c (unless otherwise noted) figure 29. load transient response i out = 500 to 1500 ma, 100 ns edge, p vin = 3 v & v out = 3.5 v figure 30. transient response during line step (3.3 v to 2.7 v in 10 s), 1 a i out step between 0 a and 1500 ma, 100 ns edge, v out = 3.5 v figure 31. line transient response p vin = 3 v to 3.6 v, 10 s edge, i out = 500 ma & v out = 5.0 v figure 32. transient response during line step (3.6 v to 3.0 v in 10 s), 1 a i out step between 0 a and 1500 ma, 100 ns edge, v out = 5.0 v v out (50 mv/div) offset: 3.5 v 20 s/div with 50 ns/pt i out (500 ma/div) v out (100 mv/div) offset: 5.0 v 20 s/div with 200 ns/pt p vin (500 mv/div) v out (500 mv/div) ac coupling 50 s/div with 2 ns/pt (infinite persistence) i out (500 ma/div) v in (1 v/div) v out (500 mv/div) ac coupling 50 s/div with 2 ns/pt (infinite persistence) i out (500 ma/div) v in (1 v/div)
ncp6868 www.onsemi.com 12 operating description general description the ncp6868 is a standalone synchronous step-up converter. it is designed primarily to boost new generation low-voltage li-ion batteries (silicon anode-like) embedded into cell and smart phones. the main function of the device is to maintain a minimum output voltage even when the battery voltage is below the system minimum. the device is capable of driving a continuous load up to 2.5 a when p vin = 2.5 v and v out = 3.5 v and operates at a switching frequency of 2.5 mhz in continuous conduction mode (ccm). the device features a boost mode coupled with a bypass mode. the bypass mode is activated when p vin is above the boost regulator?s v out set-point (low or high value set-point adjusted through vsel pin). in order to reduce the required v out supply difference between heavy and light load the v out voltage can be adjusted through vsel for anticipating a heavy load transition. this allows optimizing power consumption during wide load transitions. the bypass mode can be forced by setting the bp pin low. boost mode the ncp6868 implements an architecture that allows the device to operate in continuous conduction mode (ccm) and discontinuous conduction mode (dcm) modes and smoothly transitions between ccm and dcm. the boost architecture provides very low transient response. the ncp6868 operates in dcm mode in order to save power and improve efficiency at low loads by reducing the switching frequency. when the load increases and the current in the inductor becomes continuous, the controller automatically switches to ccm mode and switches back to dcm mode when the current in the inductor becomes discontinuous. bypass operating mode the ncp6868 has been designed to manage conditions when p vin or v bat becomes close to the required output voltage of v out . in this case the ncp6868 automatically enters the bypass operating mode (or wire mode) from boost mode and a low resistance on-state bypass (bp) mosfet is activated while the boost converter n-mosfet is turned off. the output voltage is the same as input voltage minus a drop-out voltage resulting from the resistance of the bp mosfet in parallel with the rectifier p-mosfet plus the inductor. the consequence is a resulting resistance from p vin to v out which is smaller than the resistance from the p-mosfet + inductor when in boost mode at 100% duty cycle. in this specific case the bypass mode offers a better efficiency. the device can be forced into bypass mode by setting the bp pin low. shutdown state the ncp6868 enters the shutdown state when the en pin is set low (below 0.4 v) or when the pvin pin drops below its v uvlo_fall threshold value. in this stat the current consumption of the product is the shutdown current. device power-up applying a voltage above 1.2 v to the en pin will enable the device for normal operation. a soft-start sequence is run when activating en high. it is recommended when starting up the device to maintain a dc current load below 500 ma. during device enabling current flow is prevented from p vin to v out and conversely from v out to p vin . device power up and shutdown modes are detailed in figure 33. in i 2 c mode the device is configured and programmed through the i 2 c bus once it has been powered up (after power on reset) and prior to setting the en pin high. vsel pin the vsel pin controls the device output voltage level in regards to the anticipated load or line transitions which can occur, making the output voltage transitions smoother. the v out voltage level is increased to the high value target by toggling the vsel pin from low to high. the output voltage change is transitioned to the target value in 20 s. inductor peak current limitations during normal operation, peak current limitation will monitor and limit the current through the inductor. this current limitation is particularly useful when size and/or height constrain inductor power. under-voltage lockout (uvlo) the ncp6868 core does not operate for voltages below the under voltage lock out (uvlo) level. below the v uvlo_fall threshold (typical 2.3 v), all internal circuitries (both analog and digital) are held in reset. the ncp6868 is not guaranteed to operate down to the v uvlo_fall level when the battery voltage is dropping off. to avoid erratic on/off behavior, an hysteresis is implemented. restart is guaranteed at v uvlo_rise when vbat voltage is recovering or rising.
ncp6868 www.onsemi.com 13 figure 33. start-up/shutdown diagram shutdown state no v out =v out_ok lin ss ss fault en = high ss en = low or pvin < uvlo fall bypass boost forced bp on or pv in >v out +0.1v forced bp off and pv in v out +0.1v yes w/ forced bp on or pv in >v out +0.1v yes w/ forced bp off and pv in v out +0.1v any state power good (pg) pin and thermal management features to indicate the output voltage level is established, a power good signal is available. in shutdown mode (en = low) pg is high. the power good signal is low when the dc-to-dc converter is off when en is high (during device starting up or precharge). once the output voltage reaches 95% of the expected o utput level, the power good logic signal becomes high and the open drain output becomes high impedance. during operation when the output drops below 90% of the programmed level the power good logic signal goes low (and the open drain signal transitions to a low impedance state) which indicates a power failure. when the voltage rises again to above 95% the power good signal goes high again. the power good pin can also be used as an interrupt pin operating as an over-temperature (tpgact/tpgrel), over-load or over-voltage warning function in order to prevent a potential device shutdown resulting respectively from the thermal, overload/short-circuit, or over-voltage protection. the power good signal during normal operation can be disabled by clearing the pgdcdc bit in the configuration register config2 bit d3. table 5. power-good disable-low sources interrupt name power good off events pok power good: dc-dc out of regulation or off twarn thermal warning (see tpgact & tpgrel) uvlo under voltage lock out oc over-current (ilimbp & ilimbst) ov over-voltage over current protection, bypass mode the pg pin is pulled low when the pmos current limit has triggered for more than 64 s. when this happens, the device will shut down in 0 s, 64 s, 128 s, or 256 s depending on the programmed value of (bpsctiming[1,0]). the default shutdown delay is 0 s.
ncp6868 www.onsemi.com 14 after the device shuts down, the device will attempt to restart after 20 ms. restarting will be tried 3 times before definitely shutting down in order to eliminate erratic events due to negative spikes on v out .
ncp6868 www.onsemi.com 15 over current protection, boost mode in boost mode the current protection is enabled by two separate mechanisms. when the i peak limit is triggered, boost mode will keep regulating for 2 ms and then will shut down immediately. during this period of time if the short circuit becomes active and drops the output voltage down to v in /2 then the converter will shut down immediately. therefore the device is protected in two ways based on an i peak detection timing period of 2 ms and voltage drop detection. during this process of short circuit protection the pg pin toggles high to low when v out drops below 90% of v out target. figure 34. power good (pg) behavior example p vin en v out pg rising uvlo < 2.6 v por 95% v out shut-down i.e. short circuit event 90% v out ~ 2ms over-voltage protection pg is pulled low when the v out voltage limit of 5.7 v has triggered for more than 64 s and the device will shut down. afterwards the device will attempt to restart 20 ms after. this will be tried 3 times before definitely shutting down in order to eliminate erratic events due to negative spikes on v out . thermal shutdown feature (tsd) the thermal capability of an ic can be exceeded due to the boost converter output stage power level. a thermal protection circuitry has been implemented to prevent the device from damage. this protection circuitry is only activated when the core is in active mode (output voltage is turned on). during thermal shutdown, the output voltage is turned off and the device enters shutdown mode. the thermal shutdown threshold is set at 150 c (typical) and a 20 c hysteresis has been implemented to avoid erratic on/off behavior. after a typical 150 c thermal shutdown, the ncp6868 will return to normal operation when the die temperature cools down to 130 c. this normal operation depends on the input conditions and configuration at the time the device recovers. dynamic voltage scaling (dvs) the output voltage change is operated through the i 2 c or pin vsel using a dynamic voltage scaling (dvs) approach when the required voltage change is higher than 200 mv (either by i 2 c or vsel pin). the change between set points is managed in a smooth fashion without disturbing the operation of the device under power. when programming a new output voltage that is greater than a 200 mv -increase, the output raises in steps of 200 mv every 32 s (typical) such that the dv/dt is controlled. the change rate of the voltage can be programmed as 32 s or 64 s with 32 s being the default value. the dvs sequence is automatically initiated by changing output voltage settings. there are two ways to change these settings: ? directly change the active setting register value (progvoutlow [5,0]/progvouthigh [5,0] registers) via i 2 c command ? change the vsel internal signal level by toggling vsel pin figure 35. dvs diagram v2 v1 internal reference output voltage t v interrupt control process (intsen1, intsen2, intack & intmsk registers): the interrupt controller continuously monitors internal interrupt sources, generating an interrupt signal when a system status change is detected (dual edge monitoring). individual bits generating interrupts will be set to 1 in the intack register (i 2 c read only registers), indicating the interrupt source. intack register is automatically reset by an i 2 c read. the intsen1 and intsen2 registers (read only register) contains real-time indicators of interrupt sources. all interrupt sources can be masked by writing in register intmsk. masked sources will never generate an interrupt request on pg pin (see figure 41). the pg pin is an open drain output. a non masked interrupt request will result in pg pin being driven low. when the host reads the intack registers the pg pin is released to high impedance and the interrupt register intack is cleared. figure 36 illustrates the interrupt process.
ncp6868 www.onsemi.com 16 figure 36. interrupt operation example interrupt ack register reading interrupt ack register reading interrupt ack register reading masked removed pg event i 2 c bus pg pin interrupt acknowledge (ack) register bit bx interrupt sense (sen) register bit bx (real time) interrupt mask (msk) register bit bx pg drop low event (ovp, uvlo, ilimbst, ilimbp, twrn) removed pg event i 2 c compatible interface the ncp6868 can support a subset of i 2 c protocol detailed below. the ncp6868 communicates with the external processor by means of a serial link using a 400 khz up to 3.4 mhz i 2 c two-wire interface protocol. the i 2 c interface provided is fully compatible with the standard, fast and high-speed i 2 c modes. the ncp6868 is not intended to operate as a master controller. it is under the control of the main controller (master device), which controls the clock (pin scl) and the read or write operations through sda. the i 2 c bus is an addressable interface (7-bit addressing only) featuring two read/write addresses. i 2 c communication description the first byte transmitted is the chip address (with the lsb bit set to 1 for a read operation, or set to 0 for a write operation). the following data will be: ? in case of a write operation, the register address (@reg) pointing to the register we want to write is followed by the data we will write in that location. the writing process is auto-incremental, so the first data will be written in @reg, the contents of @reg are incremented and the next data byte is placed in the location pointed to by @reg + 1 , etc. ? in case of read operation, the ncp6868 will output the data from the last register that has been accessed by the last write operation. like the writing process, the reading process is auto-incremental. figure 37. general protocol description start ic address 1 1 read ack data1 ack data n /ack stop start ack ic address 0 0 write data1 ack data n ack /ack stop from mcu to ncpxxxx from ncpxxxx to mcu read out write inside part from part if part does not acknowledge, the /nack will be followed by a stop or sr. if part acknowledges, the ack can be followed by another data or stop or sr.
ncp6868 www.onsemi.com 17 read out from part the master will first make a ?pseudo write? transaction with no data to set the internal address register. then, a stop then start or a repeated start will initiate the read transaction from the register address the initial write transaction has pointed to: figure 38. read out from part stop ic address 1 1 read ack start ic address 0 0 write register address ack start ack data1 data n ack /ack stop sets internal register pointer register address value register address + (n ? 1) value n registers read from mcu to ncpxxxx from ncpxxxx to mcu the first write sequence will set the internal pointer to the register we want access to. then the read transaction will start at the address the write transaction has initiated. transaction with real write then read with stop then start figure 39. write followed by read transaction reg + (n ? 1) value ack stop from mcu to ncpxxxx from ncpxxxx to mcu start ic address 0 0 write ack register reg 0 address ack reg value ack sets internal register pointer write value in register reg0 write value in register reg0 + (n ? 1) n registers write ic address 1 1 read start ack data1 data k ack /ack stop register reg + (n ?1) value register address + (n ? 1) + ( k ?1) value k registers read write in part write operation will be achieved by only one transaction. after chip address, the mcu first data will be the internal register we want access to, then following data will be the data we want to write in reg, reg + 1, reg + 2, , reg + n. write n registers: figure 40. write in n registers reg + (n ? 1) value ack stop from mcu to ncpxxxx from ncpxxxx to mcu start ic address 0 0 write ack register reg0 address ack reg value ack sets internal register pointer write value in register reg0 write value in register reg0 + (n ? 1) n registers write
ncp6868 www.onsemi.com 18 i 2 c address ncp6868 has four available i 2 c address selectable by factory settings (add0 to add3). different address settings can be generated upon request to on semiconductor. the default address is set to ech/edh. table 6. i 2 c address i 2 c address hex a7 a6 a5 a4 a3 a2 a1 a0 add0 w 0xe8; r 0xe9 1 1 1 0 1 0 0 r/w add1 w 0xea; r 0xeb 1 1 1 0 1 0 1 r/w add2 (default) w 0xec; r 0xed 1 1 1 0 1 1 0 r/w add3 w 0xee; r 0xef 1 1 1 0 1 1 1 r/w register map table 7 describes i 2 c registers. registers can be: r: read only register rc: read then clear (dual edge) r/w: read and write register reserved: address is reserved and register is not physically designed spare: address is reserved and register is physically designed table 7. i 2 c registers map description address register name type default function 00h rid r 00h revision identification 01h config r/w 00h configuration programming 02h progvout_low r/w 09h vout programming when vsel = low 03h progvout_high r/w 0dh vout programming when vsel = high 04h ilim r/w 03h current limit programming 05h intsen1 r 00h sense register (real time status register) 06h intsen2 r 00h sense register (real time status register) 07h intack rc 00h interrupt register 08h intmsk r/w ffh mask register to enable or disable interrupt sources (trim) 09h pid r 68h product identification 0ah fid r 00h features identification (trim) 0bh config2 r/w 07h configuration programming 2 0ch to xxh ? ? ? reserved
ncp6868 www.onsemi.com 19 registers description table 8. revision id register name: rid address: 00h type: r default: 00000000b (00h) d7 d6 d5 d4 d3 d2 d1 d0 rid_7 rid_6 rid_5 rid_4 rid_3 rid_2 rid_1 rid_0 bit bit description rid[7..0] revision identification 00000000: silicon revision 1.0 00000001: silicon revision 1.1 00000010: silicon revision 1.2 00000100: silicon revision 1.3 table 9. configuration register name: config address: 01h type: r/w default: 00000000b (00h) d7 d6 d5 d4 d3 d2 d1 d0 forcerst enable spare = 0 mode[1,0] bit bit description mode device mode of operation: 0x, 11: normal operation, auto mode 10: forced ccm mode enable[6:5] device enable modes: 00: device operation follows hardware control signal (refer to table 2) 01: device operates in auto mode regardless of the bp pin (en = 1) 10: device is forced in bypass mode regardless of the bp pin value (en = 1) 11: device is in shutdown mode. during shutdown, current flow is prevented from v in to v out and from v out to v in. all bias circuits are off forcerst force reset bit 0: normal operation. self cleared to 0 1: force reset of internal registers to default
ncp6868 www.onsemi.com 20 table 10. dc to dc output voltage programming register name: progvoutlow address: 02h type: r/w default: 00001001b (09h) d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 progvoutlow[5:0] bit bit description progvout low[5:0] sets the dc to dc converter output voltage (see table 11) default 00001001b => 3.3 v (vsel = 0) table 11. dc to dc output voltage programming progvoutlow[5:0] v out (v) @ vsel = 0 000000b 2.850 000001b 2.900 000010b 2.950 000011b 3.000 000100b 3.050 000101b 3.100 000110b 3.150 000111b 3.200 001000b 3.250 001001b 3.300 001010b 3.350 001011b 3.400 001100b 3.450 001101b 3.500 001110b 3.550 001111b 3.600 010000b 3.650 010001b 3.700 010010b 3.750 010011b 3.800 010100b 3.850 010101b 3.900 010110b 3.950 010111b 4.000 progvoutlow[5:0] v out (v) @ vsel = 0 011000b 4.050 011001b 4.100 011010b 4.150 011011b 4.200 011100b 4.250 011101b 4.300 011110b 4.350 011111b 4.400 100000b 4.450 100001b 4.500 100010b 4.550 100011b 4.600 100100b 4.650 100101b 4.700 100110b 4.750 100111b 4.800 101000b 4.850 101001b 4.900 101010b 4.950 101011b 5.000 101100b 5.050 101101b 5.100 101110b 5.150 101111b 5.200 110000b 5.250 110001b 5.300
ncp6868 www.onsemi.com 21 table 12. dc to dc output voltage programming register name: progvouthigh address: 03h type: r/w default: 00011001b (0dh) d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 progvouthigh[5:0] bit bit description progvout high[5:0] sets the dc to dc converter output voltage (see table 13) default 00001101b => 3.5 v (vsel = 1) table 13. dc to dc output voltage programming progvouthigh[5:0] v out (v) @ vsel = 1 000000b 2.850 000001b 2.900 000010b 2.950 000011b 3.000 000100b 3.050 000101b 3.100 000110b 3.150 000111b 3.200 001000b 3.250 001001b 3.300 001010b 3.350 001011b 3.400 001100b 3.450 001101b 3.500 001110b 3.550 001111b 3.600 010000b 3.650 010001b 3.700 010010b 3.750 010011b 3.800 010100b 3.850 010101b 3.900 010110b 3.950 010111b 4.000 progvouthigh[5:0] v out (v) @ vsel = 1 011000b 4.050 011001b 4.100 011010b 4.150 011011b 4.200 011100b 4.250 011101b 4.300 011110b 4.350 011111b 4.400 100000b 4.450 100001b 4.500 100010b 4.550 100011b 4.600 100100b 4.650 100101b 4.700 100110b 4.750 100111b 4.800 101000b 4.850 101001b 4.900 101010b 4.950 101011b 5.000 101100b 5.050 101101b 5.100 101110b 5.150 101111b 5.200 110000b 5.250 110001b 5.300
ncp6868 www.onsemi.com 22 table 14. peak current limit register name: ilim address: 04h type: r/w default: 00000011 (03h) d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 scpbp_dis ilim_dis spare = 0 ilim [3:0] bit bit description ilim inductor peak current settings (see table 15) ilim_dis enable/disable peak inductor current limit 0: current limit enabled 1: current limit disabled scpbp_dis enable/disable bypass short circuit protection 0: protection enabled 1: protection disabled table 15. dc to dc peak current limit programming ilim[3:0] peak current setting 0000b 2a 0001b 3a 0010b 4a ilim[3:0] peak current setting 0011b 5a 0100b 6a 0101b 7a 0110b 8a 0111b 9a table 16. interrupt sense register 1 name: intsen1 address: 05h type: r default: 00000000b (00h) d7 d6 d5 d4 d3 d2 d1 d0 sen_tsd sen_ twarn sen_ dcdcmode sen_ opmode sen_ilimbp sen_ ilimbst spare = 0 sen_pok bit bit description sen_pok power good ok sense 0: dcdc output voltage below target 1: dcdc output voltage within nominal range. this bit is set if the converter is forced in bypass mode sen_ilimbst current limit status bit (dc-dc boost mode): 0: dcdc output current is below limit 1: dcdc output current is over limit sen_ilimbp current status bit (bypass mode) 0: bypass output current is below limit 1: bypass output current is over limit sen_opmode device mode of operation status bit: 0: device operates in bypass mode 1: device operates in boost mode sen_dcdcmode dc-dc mode of operation status bit: 0: device operates in dcm mode 1: device operates in ccm mode sen_twarn thermal warning sense 0: junction temperature below thermal warning limit 1: junction temperature over thermal warning limit sen_tsd thermal shutdown sense 0: junction temperature below thermal shutdown limit 1: junction temperature over thermal shutdown limit
ncp6868 www.onsemi.com 23 table 17. interrupt sense register 2 name: intsen2 address: 06h type: r default: 00000000b (00h) d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 sen_ov sen_uvlo spare = 0 bit bit description sen_uvlo under voltage sense 0: input voltage higher than uvlo threshold 1: input voltage lower than uvlo threshold sen_ov over voltage sense 0: output voltage lower than ovp threshold 1: output voltage higher than ovp threshold table 18. interrupt acknowledge register name: intack address: 07h type: rc default: 00000000b (00h) trigger: dual edge [d7...d0] d7 d6 d5 d4 d3 d2 d1 d0 ack_tsd ack_ twarn ack_ ilimbst ack_ov ack_uvlo ack_ilimbp spare = 0 ack_pok bit bit description ack_pok power good sense acknowledgement 0: cleared 1: dcdc power good event detected ack_ilimbp bypass over current sense 0: cleared 1: bypass over current limit detected ack_uvlo under voltage sense acknowledgement 0: cleared 1: under voltage event detected ack_ov over voltage sense acknowledgement 0: cleared 1: over voltage event detected ack_ilimbst dcdc over current sense 0: cleared 1: dcdc over current limit detected ack_twarn thermal warning sense acknowledgement 0: cleared 1: thermal warning event detected ack_tsd thermal shutdown sense acknowledgement 0: cleared 1: thermal shutdown event detected
ncp6868 www.onsemi.com 24 table 19. interrupt mask register name: intmask address: 08h type: rw default: 11111111b (ffh) d7 d6 d5 d4 d3 d2 d1 d0 mask_tsd mask_ twarn mask_ ilimbst mask_ov mask_ uvlo mask_ ilimbp spare = 1 mask_pok bit bit description mask_pok power good interrupt source mask 0: interrupt is enabled 1: interrupt is masked mask_ilimbp dcdc over current interrupt source mask 0: interrupt is enabled 1: interrupt is masked mask_uvlo under voltage interrupt source mask 0: interrupt is enabled 1: interrupt is masked mask_ov over voltage interrupt source mask 0: interrupt is enabled 1: interrupt is masked mask_ilimbst dcdc over current interrupt source mask 0: interrupt is enabled 1: interrupt is masked mask_twarn thermal warning interrupt source mask 0: interrupt is enabled 1: interrupt is masked mask_tsd thermal shutdown interrupt source mask 0: interrupt is enabled 1: interrupt is masked figure 41. interruption masking logical diagram sen_tsd (r) mask_tsd (rw) sen_twarn (r) mask_twarn (rw) sen_ilimbst (r) mask_ilimbst (rw) sen_ov (r) mask_ov (rw) sen_uvlo (r) mask_uvlo (rw) sen_ilimbp (r) mask_ilimbp (rw) sen_pok (r) mask_pok (rw) pg pin pg pin will go to low state if the corresponding sense goes to 1 and if the corresponding mask is cleared.
ncp6868 www.onsemi.com 25 table 20. product id register name: pid address: 09h type: r default: 01101000b (68h) d7 d6 d5 d4 d3 d2 d1 d0 pid[7:4] pid[3:0] bit bit description pid[7..0] product identification 01101000b = 68h w/ pid[7:4] = 6, pid[3:0] = 8 table 21. firmware id register name: fid address: 0ah type: r default: 00000000b (00h) d7 d6 d5 d4 d3 d2 d1 d0 fid_7 fid_6 fid_5 fid_4 fid_3 fid_2 fid_1 fid_0 bit bit description fid[7..0] firmware identification 00000000: firmware revision 1.0 00000001: firmware revision 1.1 00000010: firmware revision 1.2 00000011: firmware revision 1.3 table 22. configuration register 2 name: config2 address: 0bh type: r/w default: 00000111 (07h) d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 bpsctiming[1,0] dvstiming pgdcdc rststatus rearm bit bit description rearm rearming of device after tsd 0: no re-arming after tsd 1: re-arming active after tsd with no reset of i 2 c registers: new power-up sequence is initiated with previously programmed i 2 c registers values rststatus reset indicator bit 0: must be written to 0 after register reset 1: default (loaded after registers reset) pgdcdc power good enabling 0 = disable 1 = enable dvstiming dvs timing change 0 = 200 mv step / 32 s 1 = 200 mv step / 64 s bpsctiming[1,0] short-circuit protection activation delay 00 = 0 s 01 = 64 s 10 = 128 s 11 = 256 s
ncp6868 www.onsemi.com 26 application information figure 42. application block diagram inductor selection the selected inductor must have high enough saturation current rating to be higher than the maximum peak current which can reach 4 a for the default configuration for a short period of time during overload situations. table 23 shows recommended inductor featuring 0.47 h of nominal value. peak-current limit inductor is used. the inductor also needs to have high enough current rating based on temperature rise concern. low dcr is good for efficiency improvement and temperature rise reduction. table 23. recommended inductors supplier part # value ( h) size (l i t) (mm) dc rated current (a) dcr max @ 25 c (m ) toko dfe201610a?r47m?t00 0.47 20 16 1 4.0 53 toko dfe201610p?r47m?t00 0.47 20 16 1 4.1 41 toko dfe201612r?r47m?t00 0.47 20 16 1.2 4.4 40 toko dfe201612p?r47m?t00 0.47 20 16 1.2 4.9 33 cyntec hmlq20161t?r47mdr?11 0.47 2.0 1.6 1.0 4.4 26 cyntec hmlq20161b?r47mdr?11 0.47 2.0 1.6 1.2 5.1 20 cyntec hmlq25201t?r47msr?11 0.47 2.5 2.0 1.0 4.3 19 tdk tfm252010a?r47m 0.47 25 20 1.0 4.5 30 tdk tfm252010ghm?r47mtaa 0.47 25 20 1.0 4.3 26 output capacitor selection the output capacitor selectio n is determin ed by the output voltage ripple and the load transient response requirement. for high transient load performance a high output capacitor value must be used. it is recommended to pay attention to the variation of the capacitor value when the bias voltage across this capacitor varies. usually the capacitor value decreases with the bias voltage and x5r/x7r low esr ceramic capacitors are recommended in order to guarantee the effective capacitor value under operating conditions. input capacitor selection one criteria for the input capacitor selection is the input voltage ripple requirement. to minimize the input voltage ripple and get better decoupling in the input power supply rail, a ceramic capacitor is recommended due to low esr and esl. the input capacitor needs also to be sufficient to protect the device from over voltage spike and a minimum of 4.7 f capacitor is required. the input capacitor should be located as close as possible to the ic. pgnd is connected to the ground terminal of the input cap which then connects to the ground plane. the p vin is connected to the v bat terminal of the input capacitor which then connects to the v bat plane. layout and pcb design recommendations good pcb layout helps high power dissipation from a small package with reduced temperature rise. thermal layout guidelines are:
ncp6868 www.onsemi.com 27 ? a four or more layers pcb board with solid ground planes is preferred for better heat dissipation. ? adding extra vias around the ic is encouraged to connect the inner ground layers to reduce thermal impedance. ? use large area copper especially in the top layer to help thermal conduction and radiation. ? use two layers for the high current paths (p vin , pgnd, sw, v out ) in order to split current in two different paths and limit pcb copper self heating. (see demo board example figure 43) figure 43. layout minimum recommended occupied space 2520 2. 5 x 2.0 mm 0603 1.6 x 0.8 m m pvin vout en vsel rst / pg bp mode/ scl nc/sda sw agnd pgnd pgnd pvin vout sw pgnd 06 03 1.6 x0.8mm 3.8 mm 4.1 mm s < 16 mm 2 the input capacitor is placed as close as possible to the ic. p vin is directly connected to the c in input capacitor, and then connected to the p vin plane. local mini planes are used on the top layer (green) and layer just below top layer with laser vias. pgnd is directly connected to the c in input capacitor, and then connected to the gnd plane. local mini planes are used on the top layer (green) and layer just below top layer with laser vias. sw is connected to the lx inductor with local mini planes used on the top layer (green) and layer just below top layer with laser vias. v out is directly connected to the c out output capacitor and then connected to the pgnd plane. figure 44. example of pcb implementation table 24. ordering information device* package shipping ? NCP6868PFCCT1G wlcsp16 (pb-free) 3000 / tape & reel ncp6868v315fcct1g wlcsp16 (pb-free) 3000 / tape & reel ncp6868v330fcct1g wlcsp16 (pb-free) 3000 / tape & reel ncp6868e315fcct1g wlcsp16 (pb-free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. * consult sales office for specific output voltage requirement
ncp6868 www.onsemi.com 28 package dimensions wlcsp16 1.80x1.80 case 567ju issue o seating plane 0.25 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x a 0.05 b c 0.03 c 0.08 c 16x b d 2 3 4 0.10 c a1 a c 0.25 16x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.25 c 2x top view side view bottom view note 3 e recommended package outline abc pitch 1 pitch a1 e/2 a2 dim a min max ??? millimeters a1 d 1.80 bsc e b 0.24 0.29 e 0.40 bsc 0.60 0.17 0.23 1.80 bsc a2 0.36 ref e/2 p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp6868/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.

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